3D integration (3DI) comprises a device system integration method that brings heterogeneous devices together in close proximity so that they function as a homogeneous device. 3DI is different than traditional 2D planar back-end-of-line (BEOL) integration in that 3DI adds an additional dimension, (Z) integration, which not only allows more devices from different sources and types to be integrated into the system in close proximity, but also enables them to function as a unit.
This integration allows more device content (more memories) and faster access times (shorter distances) than simple scaling can achieve in the traditional 2D planar device. To increase device system speed the clock-cycle distance is a critical domain for functionality, requiring it to be within the system. A clock-cycle distance comprises the distance that the signal can cover within one device clock-cycle. For today's devices running at over several GHz speed this distance is reduced to only several millimeters.
In a 2D configuration more and more device contents have to be placed outside this area and more clock-cycles are needed to access them, and as a result, increases access time (or slower speed). Multi-core is one of the ways to keep the logic and memory within a short distance locally to each core while using parallelism to enable the continued scaling. 3D architecture can further enhance the memory density to each core with a shorter connection distance between the core and memory by introducing additional contents from the 3rd dimension (Z-stack), which therefore increases the device functionality while maintaining the components within the critical clock-cycle zone. In addition to more contents within the clock-cycle zone, 3DI also allows additional components (such as SiGe, a III-V device, opto-electronics, MEMS), to be integrated as part of the device systems in the device level. A III-V device comprises a device based on at least one element selected from Group IIIB of the Periodic Table of Elements and at least one element selected from Group VB of the Periodic Table of Elements, where the Periodic Table comprises the IUPAC form. An example of these materials comprises GaAs. Ga is in column IIIB and As in column VB of the Periodic Table. III-V devices normally run faster (higher mobility) than Si or Ge devices. Both Si and Ge are in column IVB of the Periodic Table and have less stress in the bond.
Of the process format, 3DI can be further separated into chip level and wafer-level integration. The chip-level 3DI mainly focus on lower density I/O (input/output) (dozens to hundreds of I/Os) and slower system where high contents and lower power within a given footprint comprises the key consideration for the consumer markets. The wafer-level 3DI focus more on high performance systems where I/O density is in the thousands, operates at high speeds (>GHz), and the system clock-distance becomes a key requirement. In this high performance area through-Si connection becomes a dominant factor to reduce distance between the devices.
Of the integration scheme, 3DI can further separate into chip stacking and through-Si connection. For most chip-level 3DI the Z-connection is through device edge leads. The edge leads are then connected to a logic wafer with wire bonds. Due to such connection scheme, a chip-level connection can give more content at a slower speed. Also, it is difficult to supply power to the stacked system stack.
3Di through-Si connection allows the integration at wafer level and offers a higher I/O density and a close Z-connection. Through-Si can also be further separated into via-first and via last approaches. Via-first normally allows a higher wiring contents since the I/Os do not go through the top device directly and gives more area for wiring. The level-level z-connections are typically done in metal compression bond (Such as Cu—Cu, no solder, no adhesive), micro-C4 (solder, no adhesive), or transfer joining (“T&J,” or “TJ” metal compression and adhesive composite, hybrid bonding known in the art). Via-first connections typically have a higher wiring density (BEOL interconnection) and an I/O density of about 5 to about 10 mu pitch mu.
U.S. Pat. No. 6,355,501 illustrates a via-first configuration on element 100, where the level-level connection is through imbeded vias. (Since via-first does not impact the wiring levels for the top wafer, the wiring density is normally higher for the via-first approach). The interface contact is through mechanical means so the interface via density is typically about 5 to about 10 um (micron) at the best. U.S. Pat. No. 7,312,487 illustrates the via-last option, element 172, where the wafers are stacked first and then vias are formed through the entire top wafer. Since the vias are lithographically defined, this via-last has a higher density of via counts, at about 1 um. Since the Through-Si vias in the top wafer take up wiring channels, the wing density is reduced for via-last.
Since the through-Si vias in the top wafer take up wiring channels, the wiring density is reduced for via-last, about 10 um pitch. For 3DI with via-last approach, the wiring density typically is reduced due to the use of the wiring channels by the through-Si vias through the entire device stack (via-first allows z-wiring and reduces the loss of channels). Since the through-Si vias can be defined lithographically, via-last normally have a higher via-density (under about 1 um pitch) than via-first approach (about 5 to about 10 um pitch).
In all 3DI integration schemes mentioned above, the cooling of the system is typically a difficult issue to resolve. The tighter stacks of devices generate more heat density but with reduced heat dissipation. Some work in micro-channels cooling for 3DI only limits the cooling through surface layer and is difficult to achieve an effective cooling with more stacks involved in the 3D systems.
One particular issue associated with 3DI through-Si connections comprises the ESD (electro-static discharge) protection load. In any device production an EDS protection circuitry is designed and linked to a I/O net. This is to protect it from manufacturing process ESD. Since each wafer for 3DI needs their ESD the final 3DI circuits will have a total ESD as large as the sum of all the devices in the 3DI device. This can be a large load as the number of devices increase and requires a large driver to access the 3DI circuits which could significantly slow them down.
In 3DI by either chip stacking or through-Si connection, the heating density increases as the number of 3DI devices increase. This limits the number of 3DI devices as the heat dissipation become a road block for further 3D content increase.
U.S. Pat. Nos. 5,702,984; 5,432,729; 5,561,622; 5,502,667; 5,347,428; 6,717,061; and 7,193,304 illustrate edge connection details of some of the chip stacking methods. Note that all chip stacking methods have no cooling channels proposed and have signal and power accesses only through wire-bonding.
U.S. Pat. Nos. 7,132,754; 6,908,792; and 6,473,308 illustrate chip stacking by wrap-around with a signal bus. This type connection also had long I/O length. U.S. Pat. Nos. 7,193,304; 7,151,009; 7,07,1546; 7,005,730; 6,355,501 (metal/oxide); 6,821,826 (oxide-oxide); 5,804,004; 7,312,487; 7,307,003; and; 7,056,813 illustrate common Through-Si via connections.
U.S. Pat. No. 6,355,501 illustrates a via-first configuration on element 100, where the level-level connection is through imbeded vias. Since via-last does not impact the wiring levels for the top wafer, the wiring density is normally higher for the via-first approach. The interface contact is through mechanical means so the interface via density is typically about 5 to about 10 um at the best. U.S. Pat. No. 7,312,487 illustrates the via-last option, element 172, where the wafers are stacked first and then vias are formed through the entire top wafer. Since the vias are lithographically defined, this via-last has a higher density of via counts, at about 1 um. Since the Through-Si vias in the top wafer take up wiring channels, the wiring density is reduced for via-last.
U.S. Pat. Nos. 7,355,277; 7,230,334; 7,170,164; and 6,388,317 illustrate micro-channels cooling.
U.S. Pat. Nos. 6,864,165; 6,856,025; 6,599,778; 7,071,031; 6,835,589; 6,640,021; 7,049,697; 6,737,297; 6,444,560; 6,329,609; 6,600,224; 6,090,633; 6,678,949; and 6,281,452 illustrate T&J 3DI polyimide stud via joining connections (lock and key) on chip devices.
The scientific literature also describe some of these devices and processes for making them, and include:    H. B. Pogge et al., Proc. AMC 2001, pp. 129-136;    M. Despont, et al; TRANSDUCERS, Solid-State Sensors, Actuators and Microsystems, 12th International Conference on, 2003, Volume 2, 8-12 Jun. 2003, pp. 1907-1910;    K. W. Guarini, et al; IEMD 2002 pp. 943-945.    R. Yu, Proc. VMIC 2007, p. 223, 2007.    P. Kogge et al., ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems; Information Processing Techniques Office, Air Force Research Laboratory, Sep. 28, 2008; pp. 159, 161.
These prior art devices and methods of assembling and using them have proved successful, however, they also present several issues, such as for example in chip stacking, edge connection leads to signal delay, lower I/O density, difficulties in powering the system and difficulties in cooling the system in high power applications.
Similarly, the current through-Si 3D wafer stacking processes and resultant devices present issues, e.g., thin Si construction (20 um) requires stacking wafers one at a time to allow through-Si vias; it is difficult to make the via less than 5 um in size and 10 um in pitch in devices employing Cu; through-Si vias can be made from W but W has a higher resistivity than Cu; through-vias pass through the bonding interface making bonding defects difficult to control; wafer stacks are limited due to bonding thermal cycles; the process is complex and introduces via yield and wafer yield issues; manufacturing involves long process cycles; wafer level distortions are introduced; it is difficult to cool the system; and it is difficult to dissipate power.